Comparison of ARM processors: Difference between revisions

{{More citations needed|talk=References and intro|date=June 2014}}

This is a comparison of processors based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name.

== ARMv6 ==

|}

== ARMv7-A ==

{{Use dmy dates|date=August 2016}}

This is a table comparing [[central processing unit]]s which implement the '''[[ARMv7-A]]''' (A means Application<ref name=ARM-V7-differences>{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16827.html|website=infocenter.arm.com|publisher=ARM Information Center|access-date=1 June 2016|title=ARM V7 Differences}}</ref>) [[instruction set architecture]] and mandatory or optional extensions of it, the last [[AArch32]].

{{Expand list|date=February 2014}}

{|class="wikitable sortable" style="text-align:center; font-size:94%"

!core!!decode<br>width!!execution<br>ports!![[Instruction pipeline|pipeline]]<br>depth!![[Out-of-order execution]]!![[Floating-point unit|FPU]]<!-- -D16/-D32 stands for number of registers-->!!pipelined<br>VFP!!FPU<br>registers!![[ARM NEON|NEON]]<br>(SIMD)!![[ARM big.LITTLE|big.LITTLE]]<br>role!!virtualization<ref name=Virtualization-support/>!![[Semiconductor device fabrication|process<br>technology]]!!L0<br>cache!!L1<br>cache!!L2<br>cache!!core<br>configurations!!speed<br>per<br>core<br>([[Dhrystone#Results|DMIPS<br>/ MHz]])!!ARM part number<br>(in the main ID register)

![[ARM Cortex-]]

|{{|}}|| ||8||{{No}}

|{{|VFPv4}} ||{{|16 × 64-bit||{{|64-bit wide}}

|{{no}}

|{{No}}

|40/28&nbsp;nm

| ||4–64&nbsp;[[Kibibyte|KiB]] / core||

|1, 2, 4

|1.57

|0xC05

![[ARM Cortex-]]

|{{|2}}|| ||||{{No}}

|{{|}}||{{}}|| × 64-bit||{{|64-bit wide}}

|{{Yes|LITTLE}}

|{{Yes|Yes}} <ref name=Cortex-A7/>

|40/28&nbsp;nm

| ||8–64&nbsp;KiB / core||up to 1&nbsp;[[Mebibyte|MiB]] (optional)

|1, 2, 4, 8

|1.9

|0xC07

![[ARM Cortex-]]

|{{|2}}|| ||||{{}}

|{{Partial|VFPv3}}||{{}}||32 × 64-bit||{{|64-bit wide}}

|{{No}}

|{{No}}

|65/55/45&nbsp;nm

| ||32&nbsp;KiB + 32&nbsp;KiB||256 or 512 (typical)&nbsp;KiB

|1

|2.0

|0xC08

![[ARM Cortex-]]

|{{|}}|| || ||{{Yes}}

|{{|}}||{{Yes}}|| 32 × 64-bit||{{|-bit wide}}

|{{Partial|Companion Core}}

|{{No}} <ref name=Cortex-A9/>

|65/45/40/32/28&nbsp;nm

| ||32&nbsp;KiB + 32&nbsp;KiB||1&nbsp;MiB

|1, 2, 4

|2.5

|0xC09

![[ARM Cortex-]]

|{{|}}|| ||||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||32 × 64-bit||{{|128-bit wide}}

|{{No}} <ref>{{Cite web|url=http://community.arm.com/groups/processors/blog/2014/09/30/arm-cortex-a17-cortex-a12-processor-update|title = ARM Cortex-A17 / Cortex-A12 processor update - Architectures and Processors blog - Arm Community blogs - Arm Community}}</ref>

|{{Yes}}

|28&nbsp;nm

| ||32-64&nbsp;KiB + 32&nbsp;KiB||256&nbsp;KiB, to 8&nbsp;MiB

|1, 2, 4

|3.0

|0xC0D

![[ARM Cortex-]]

|{{|}}|| ||||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||32 × 64-bit||{{|128-bit wide}}

|{{}}

|{{Yes|Yes}} <ref name=Cortex-A15/>

|32/28/20&nbsp;nm

| ||32&nbsp;KiB + 32&nbsp;KiB per core||up to 4&nbsp;MiB per cluster, up to 8&nbsp;MiB per chip

|2, 4, 8 (4×2)

|3.5 to 4.01

|0xC0F

![[ARM Cortex-A17]]

|{{Maybe|2}} <ref name=Cortex-A17/>|| ||11+||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||{{good|32 × 64-bit}}||{{Good|128-bit wide}}

|{{Yes|big}}

|{{Yes}}

|28&nbsp;nm

| ||32&nbsp;KiB + 32&nbsp;KiB per core||256&nbsp;KiB, up to 8&nbsp;MiB

|up to 4

|4.0

|0xC0E

![[Scorpion (processor)|Qualcomm Scorpion]]

|{{Maybe|2}}||3 <ref name=Snapdragon-Krait/>||10||{{Partial|Yes (FXU&LSU only) <ref>{{Cite web |url=http://rtcgroup.com/arm/2007/presentations/253%20-%20ARM_DevCon_2007_Snapdragon_FINAL_20071004.pdf |title=Qualcomm High Performance Processor Core and Platform for Mobile Applications |first=Lou |last=Mallia |date=2007 |access-date=8 May 2014 |archive-date=26 April 2017 |archive-url=https://web.archive.org/web/20170426061946/http://rtcgroup.com/arm/2007/presentations/253%20-%20ARM_DevCon_2007_Snapdragon_FINAL_20071004.pdf |url-status=dead }}</ref>}}

|{{Partial|VFPv3}}||{{Yes}}|| ||{{Good|128-bit wide}}

|{{No}}

|

|[[65 nanometer|65]]/[[45 nanometer|45&nbsp;nm]]

| ||32&nbsp;KiB + 32&nbsp;KiB||256&nbsp;KiB (single-core)<br>512&nbsp;KiB (dual-core)

|1, 2

|2.1

|0x00F

![[Krait (processor)|Qualcomm Krait]]<ref>{{Cite web|url=http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture|title = Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored}}</ref>

|{{Good|3}}||7||11||{{Yes}}

|{{Yes|VFPv4 <ref>{{Cite web|url=http://www.anandtech.com/show/5559/qualcomm-snapdragon-s4-krait-performance-preview-msm8960-adreno-225-benchmarks/2|title = Qualcomm Snapdragon S4 (Krait) Performance Preview - 1.5 GHZ MSM8960 MDP and Adreno 225 Benchmarks}}</ref>}}||{{Yes}}|| ||{{Good|128-bit wide}}

|{{No}}

|

|28&nbsp;nm

|4&nbsp;KiB + 4&nbsp;KiB direct mapped||16&nbsp;KiB + 16&nbsp;KiB 4-way set associative||1&nbsp;MiB 8-way set associative (dual-core) / 2&nbsp;MiB (quad-core)

|2, 4

|3.3 (Krait 200)<br>3.39 (Krait 300)<br>3.39 (Krait 400)<br>3.51 (Krait 450)

|0x04D<br><br>0x06F

![[Apple A6|Swift]]

|{{Good|3}}||5||12||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||{{good|32 × 64-bit}}||{{Good|128-bit wide}}

|{{No}}

|

|32&nbsp;nm

| ||32&nbsp;KiB + 32&nbsp;KiB||1&nbsp;MiB

|2

|3.5

|?

|-

!core

!decode<br>width

!execution<br>ports

![[Instruction pipeline|pipeline]]<br>depth

![[Out-of-order execution]]

![[Floating-point unit|FPU]]<!-- -D16/-D32 stands for number of registers-->

!pipelined<br>VFP

!FPU<br>registers

![[ARM NEON|NEON]]<br>(SIMD)

![[ARM big.LITTLE|big.LITTLE]]<br>role

!virtualization<ref name="Virtualization-support" />

![[Semiconductor device fabrication|process<br>technology]]

!L0<br>cache

!L1<br>cache

!L2<br>cache

!core<br>configurations

!speed<br>per<br>core<br>([[Dhrystone#Results|DMIPS<br>/ MHz]])

!ARM part number<br>(in the main ID register)

== ARMv8-A ==

{{Use dmy dates|date=August 2016}}

This is a table of [[64-bit computing|64]]/32-bit [[central processing unit]]s which implement the '''[[ARMv8-A]]''' [[instruction set architecture]] and mandatory or optional extensions of it. Most chips support the [[32-bit]] [[ARMv7-A]] for legacy applications. All chips of this type have a [[floating-point unit]] (FPU) that is better than the one in older ARMv7-A and [[ARM Architecture#Advanced SIMD (NEON)|NEON]] ([[Single instruction, multiple data|SIMD]]) chips. Some of these chips have [[coprocessors]] also include cores from the older [[32-bit]] architecture (ARMv7). Some of the chips are [[System on a chip|SoCs]] and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung [[Exynos]] 7 Octa.

{{expand list|date=May 2014}}

{| class="wikitable sortable" style= text-align:center;"

! rowspan="2" | Company

! rowspan="2" | Core

! rowspan="2" | Released

! rowspan="2" | Revision

! rowspan="2" | Decode

! rowspan="2" | [[Instruction pipeline|Pipeline]]<br />depth

! colspan="2" | [[Out-of-order execution|Out-of-order<br />execution]]

! rowspan="2" | [[Branch predictor|Branch<br />prediction]]

! [[ARM |]]

! rowspan="2" | Exec.<br />ports

! rowspan="2" | [[SIMD instruction|SIMD]]

! | [[ |]]<br />(in [[|]])

! rowspan="2" | [[Simultaneous multithreading|Simult. MT]]

! cache

! rowspan="2" | [[CPU cache|L1 cache]]<br />[[Instruction cache|Instr]]&nbsp;+&nbsp;[[Data cache|Data]]<br />(in [[Kibibyte|KiB]])

! rowspan="2" | L2 cache

! rowspan="2" | L3 cache

! rowspan="2" | Core<br />configu-<br />rations

! rowspan="2" | [[Dhrystone#Results|DMIPS/<br />MHz]]{{refn|group=note|name=first|As [[Dhrystone]] (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.}}

! rowspan="2" | ARM part number (in the main ID register)

!Have it

!Entries

! rowspan="16" | [[ARM Ltd.]]

! [[ARM Cortex-A32|Cortex-A32 (32-bit)]]<ref>{{cite news|last1=Frumusanu|first1=Andrei|title=ARM Announces Cortex-A32 IoT and Embedded Processor|url=http://www.anandtech.com/show/10061/arm-announces-cortex-a32|access-date=13 June 2016|publisher=Anandtech.com|date=22 February 2016}}</ref>

| 2017

| ARMv8.0-A<br /><small>(only [[32-bit]])</small> || 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}

| 28<ref>{{Cite web|url=https://www.arm.com/about/newsroom/new-ultra-efficient-arm-cortex-a32-processor-expands-embedded-and-iot-portfolio.php|title=New Ultra-efficient ARM Cortex-A32 Processor Expands… - ARM|website=www.arm.com|access-date=2016-10-01}}</ref>

| {{No}} || {{No}} || 8–64 + 8–64 || 0–1&nbsp;MiB || {{No}} || 1-4+ || {{dunno}} || 0xD01

![[Arm Cortex-A34|Cortex-A34 (64-bit)]]<ref>{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34|title=Cortex-A34|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-10-10}}</ref>

| 2019

|ARMv8.0-A<br /><small>(only [[64-bit computing|64-bit]])</small>|| 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}

| {{dunno}} || {{No}} || {{No}} ||8–64 + 8–64 || 0–1&nbsp;MiB || {{No}} || 1-4+ || {{dunno}} || 0xD02

|-

! [[ARM Cortex-A35|Cortex-A35]]<ref name="cortex-a35">{{cite web|title=Cortex-A35 Processor|url=https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php|website=ARM|publisher=ARM Ltd}}</ref>

| 2017

| ARMv8.0-A || 2-wide<ref>{{cite web|url=http://anandtech.com/show/9769/arm-announces-cortex-a35|title=ARM Announces New Cortex-A35 CPU - Ultra-High Efficiency For Wearables & More|first=Andrei|last=Frumusanu}}</ref>|| 8 || {{No}} || 0 || {{Yes}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}

| 28&nbsp;/&nbsp;16&nbsp;/<br />14&nbsp;/&nbsp;10 || {{No}} || {{No}} || 8–64 + 8–64 || 0 / 128&nbsp;KiB–1&nbsp;MiB || {{No}} || 1–4+ || 1.78 || 0xD04

|-

! [[ARM Cortex-A53|Cortex-A53]]<ref name="a53-page">{{cite web|title=Cortex-A53 Processor|url=http://www.arm.com/products/processors/cortex-a/cortex-a53-processor.php|website=ARM|publisher=ARM Ltd}}</ref>

| 2014

| ARMv8.0-A || 2-wide || 8 || {{No}} || 0 || rowspan="2" | Conditional+<br />Indirect branch<br />prediction || {{Yes|big/LITTLE}} || 2 || {{dunno}}

| 28&nbsp;/&nbsp;20&nbsp;/<br />16&nbsp;/&nbsp;14&nbsp;/&nbsp;10 || {{No}} || {{No}} || 8–64 + 8–64 || 128&nbsp;KiB–2&nbsp;MiB || {{No}} || 1–4+ || 2.24 || 0xD03

|-

! [[ARM Cortex-A55|Cortex-A55]]<ref name="a55-page">{{cite news|last1=Matt|first1=Humrick |title=Exploring DynamIQ and ARM's New CPUs: Cortex-A75, Cortex-A55|url=http://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55|access-date=29 May 2017|publisher=Anandtech.com|date=29 May 2017}}</ref>

| 2017

| ARMv8.2-A || 2-wide || 8 || {{No}} || 0 || {{Yes|big/LITTLE}} || 2 || {{dunno}}

| 28&nbsp;/&nbsp;20&nbsp;/<br />16&nbsp;/&nbsp;14&nbsp;/&nbsp;12&nbsp;/&nbsp;10&nbsp;/&nbsp;5<ref name="a55-5nm">{{cite web|title=Qualcomm Snapdragon 888 5G Mobile Platform |url=https://www.qualcomm.com/products/snapdragon-888-5g-mobile-platform|access-date=6 January 2021}}</ref>

| {{No}} || {{No}} || 16–64 + 16–64 || 0–256&nbsp;KiB/core || {{Yes|0–4&nbsp;MiB}} || 1–8+ || 2.65<ref name="a55-perf">Based on 18% perf. increment over Cortex-A53 {{cite web|title=Arm Cortex-A55: Efficient performance from edge to cloud|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-a55-efficient-performance-from-edge-to-cloud|website=ARM|publisher=ARM Ltd}}</ref>

|0xD05

|-

! [[ARM Cortex-A57|Cortex-A57]]<ref>{{Cite web|url=https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review|title=ARM A53/A57/T760 investigated - Samsung Galaxy Note 4 Exynos Review|last=Smith|first=Andrei Frumusanu, Ryan|website=www.anandtech.com|access-date=2019-06-17}}</ref>

| 2013

| ARMv8.0-A || 3-wide || 15 || {{Yes}}<br /> 3-wide dispatch || {{dunno}} || {{dunno}} || {{Yes|big}} || 8 || {{dunno}}

| 28&nbsp;/&nbsp;20&nbsp;/<br />16<ref name="TSMC-HiSilicon-16nm" />&nbsp;/&nbsp;14 || {{No}} || {{No}} || 48 + 32 || 0.5–2&nbsp;MiB || {{No}} || 1–4+ || 4.8 ||0xD07

|-

! [[ARM Cortex-A65|Cortex-A65]]<ref name="arm-cortexa65">{{cite web|title=Cortex-A65 - Arm Developer|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65|website=ARM Ltd.|access-date=14 July 2020}}</ref>

|2019

| ARMv8.2-A || {{dunno}} || {{dunno}} || {{Yes}}

| || {{Yes|Two-level}} || {{dunno}} || 2

| || {{dunno}}

|No

|No|| {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}}

|0xD06

|-

! [[ARM Cortex-A65AE|Cortex-A65AE]]<ref name="arm-cortexa65ae">{{cite web|title=Cortex-A65AE - Arm Developer|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae|website=ARM Ltd.|access-date=26 April 2019}}</ref>

|2019

| ARMv8.2-A || {{dunno}} || {{dunno}} || {{Yes}}

| || {{Yes|Two-level}} || {{dunno}} || 2

| || {{dunno}}

|SMT2

|No|| 16-64 + 16-64 || 64-256&nbsp;KiB || 0-4&nbsp;MB || 1–8 || {{dunno}}

|0xD43

|-

! [[ARM Cortex-A72|Cortex-A72]]<ref name="anand-coretexa72">{{cite web|last1=Frumusanu|first1=Andrei|title=ARM Reveals Cortex-A72 Architecture Details|url=http://www.anandtech.com/show/9184/arm-reveals-cortex-a72-architecture-details|website=Anandtech|access-date=25 April 2015}}</ref>

| 2015

| ARMv8.0-A || 3-wide || 15

|{{Yes}}<br /> 5-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}} || 8

| || 28&nbsp;/&nbsp;16

|No

|No|| 48 + 32 || 0.5–4&nbsp;MiB || No || 1–4+ ||6.3-7,3<ref name="users.nik.uni-obuda.hu" />

|0xD08

|-

! [[ARM Cortex-A73|Cortex-A73]]<ref>{{cite news|last1=Frumusanu|first1=Andrei|title=The ARM Cortex A73 - Artemis Unveiled|url=http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled|access-date=31 May 2016|publisher=Anandtech.com|date=29 May 2016}}</ref>

| 2016

| ARMv8.0-A || 2-wide || 11–12

|{{Yes}}<br /> 4-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}} || 7

| || 28&nbsp;/&nbsp;16&nbsp;/&nbsp;10

|No

|No|| 64 + 32/64 || 1–8&nbsp;MiB || No || 1–4+ || 7.4-8.5<ref name="users.nik.uni-obuda.hu" />

|0xD09

|-

![[ARM Cortex-A75|Cortex-A75]]<ref name="a55-page" />

|2017

|ARMv8.2-A

|3-wide

|11–13

|{{Yes}}<br /> 6-wide dispatch

|

|{{Yes|Two-level}}

|{{Yes|big}}

|8?

|2*128b

|28&nbsp;/&nbsp;16&nbsp;/&nbsp;10

|No

|No

|64 + 64

|256–512&nbsp;KiB/core

|0–4&nbsp;MiB

|1–8+

|8.2-9.5<ref name="users.nik.uni-obuda.hu">http://users.nik.uni-obuda.hu/sima/letoltes/Processor_families_Knowledge_Base_2019/ARM_processors_lecture_2018_12_02.pdf {{Bare URL PDF|date=March 2022}}</ref>

|0xD0A

|-

![[ARM Cortex-A76|Cortex-A76]]<ref name="anand">{{cite news |last1=Frumusanu |first1=Andrei |title=ARM Cortex-A76 CPU Unveiled |url=https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse |access-date=1 June 2018 |publisher=Anandtech |date=31 May 2018}}</ref>

|2018

|ARMv8.2-A

|4-wide

|11–13

|{{Yes}}<br /> 8-wide dispatch

|128|| {{Yes|Two-level}} || {{Yes|big}} || 8

|2*128b

|10 / 7

|No

|No

|64 + 64

|256–512&nbsp;KiB/core

|1–4&nbsp;MiB

|1–4

|10.7-12.4<ref name="users.nik.uni-obuda.hu"/>

|0xD0B

|-

![[ARM Cortex-A76AE|Cortex-A76AE]]<ref name="arm-cortexa76ae">{{cite web|title=Cortex-A76AE - Arm Developer|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76ae|website=ARM Ltd.|access-date=14 July 2020}}</ref>

|2018

|ARMv8.2-A

|{{dunno}}

|{{dunno}}

|{{Yes}}

|128

|{{Yes|Two-level}}

|{{Yes|big}}

|{{dunno}}

|

|{{dunno}}

|No

|No

|{{dunno}}

|{{dunno}}

|{{dunno}}

|{{dunno}}

|{{dunno}}

|0xD0E

|-

![[Cortex-A77]]<ref>{{Cite web|url=https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance/|title=Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance|last=Schor|first=David|date=2019-05-26|website=WikiChip Fuse|language=en-US|access-date=2019-06-17}}</ref>

|2019

|ARMv8.2-A

|4-wide

|11–13

|{{Yes}}<br /> 10-wide dispatch

|160|| {{Yes|Two-level}} || {{Yes|big}}

|12

|2*128b

|7

|No

|1.5K entries

|64 + 64

|256–512&nbsp;KiB/core

|1–4&nbsp;MiB

|1-4

|13-16<ref>According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017</ref>

|0xD0D

|-

![[ARM Cortex-A78|Cortex-A78]]<ref>{{Cite web|title=Arm Unveils the Cortex-A78: When Less Is More|url=https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more/|date=2020-05-26|website=WikiChip Fuse|language=en-US|access-date=2020-05-28}}</ref><ref>{{Cite web|title=Cortex-A78|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2020-05-28}}</ref>

|2020

|ARMv8.2-A

|4-wide

|

|{{Yes}}

|160

|Yes

|{{Yes|big}}

|13

|2*128b

|

|No

|1.5K entries

|32/64 + 32/64

|256–512&nbsp;KiB/core

|1–4&nbsp;MiB

|1-4

|{{dunno}}

|0xD41

|-

![[ARM Cortex-X1|Cortex-X1]]<ref name=":2">{{Cite web|title=Introducing the Arm Cortex-X Custom program|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-x-custom-program|website=community.arm.com|language=en|access-date=2020-05-28}}</ref>

|2020

|ARMv8.2-A

|5-wide<ref name=":2" />

|{{dunno}}

|{{yes}}

|224

|Yes

|{{Yes|big}}

|15

|4*128b

|

|No

|3K entries

|64 + 64

|up to 1 MiB<ref name=":2" />

|up to 8 MiB<ref name=":2" />

|custom<ref name=":2" />

|{{dunno}}

|0xD44

|-

! rowspan="17" |[[Apple Inc.]]

![[Cyclone (microarchitecture)|Cyclone]]<ref name="AnandTech-iPhone5s-64-bit" />

| 2013

| ARMv8.0-A || 6-wide<ref name="AnandTech-Cyclone" />|| 16<ref name="AnandTech-Cyclone" />|| {{Yes}}<ref name="AnandTech-Cyclone" />

|192|| {{Yes}} || {{No}} || 9<ref name="AnandTech-Cyclone" />

| || 28<ref name="Chipworks-A7" />

|No

|No|| 64 + 64<ref name="AnandTech-Cyclone" />|| 1&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 4&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 2<ref name="AnandTech-iPhone5s-A7" />|| 1.3-1.4&nbsp;GHz

|

|-

! [[Typhoon (microarchitecture)|Typhoon]]

| 2014

| ARMv8.0‑A || 6-wide<ref name="AnandTech-Twister" />|| 16<ref name="AnandTech-Twister" />|| {{Yes}}<ref name="AnandTech-Twister" />

| || {{Yes}} || {{No}} || 9

| || 20

|No

|No|| 64 + 64<ref name="AnandTech-Cyclone" />|| 1&nbsp;MiB<ref name="AnandTech-Twister" />|| 4&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 2, 3 (A8X) || 1.1-1.5&nbsp;GHz

|

|-

! [[Twister (microarchitecture)|Twister]]

| 2015

| ARMv8.0‑A || 6-wide<ref name="AnandTech-Twister" />|| 16<ref name="AnandTech-Twister" />|| {{Yes}}<ref name="AnandTech-Twister" />

| || {{Yes}} || {{No}} || 9

| || 16&nbsp;/&nbsp;14

|No

|No|| 64 + 64<ref name="AnandTech-Twister" />|| 3&nbsp;MiB<ref name="AnandTech-Twister" />|| 4&nbsp;MiB<ref name="AnandTech-Twister" /><br />No ([[Apple A9X|A9X]])|| 2 || 1.85-2.26&nbsp;GHz

|

|-

![[Apple A10|Hurricane]]

|rowspan="2"|2016

|ARMv8.0‑A

|6-wide<ref name="A10 6-wide">{{cite web|url=https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/3|title=Apple had shifted the microarchitecture in Hurricane (A10) from a 6-wide decode from to a 7-wide decode|publisher=AnandTech|date=October 5, 2018}}</ref>

|16

|{{Yes}}

|

|

|{{Yes|"big" <small>(In [[Apple A10|A10]]/[[Apple A10X|A10X]] paired with "LITTLE" [[Apple A10|Zephyr]]<br />cores)</small>}}

|9

|3*128b

|16 ([[Apple A10|A10]])<br />10 ([[Apple A10X|A10X]])

|No

|No

|64 + 64<ref name=":0">{{Cite web|url=http://system-on-a-chip.specout.com/l/1223/Apple-A10-Fusion|title=Apple A10 Fusion|website=system-on-a-chip.specout.com|access-date=2016-10-01}}{{Dead link|date=July 2019 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>

|3 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />8 MiB ([[Apple A10X|A10X]])

|4 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />No ([[Apple A10X|A10X]])

|2x [[Apple A10 Fusion|Hurricane]] (A10) <br /> 3x [[Apple A10 Fusion|Hurricane]] (A10X)

|2.34-2.36&nbsp;GHz

|

|-

![[Apple A10|Zephyr]]

|ARMv8.0‑A

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|16 ([[Apple A10|A10]])<br />10 ([[Apple A10X|A10X]])

|No

|No

|32 + 32<ref name="A11_A12_caches" />

|1&nbsp;MiB

|4 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />No ([[Apple A10X|A10X]])

|2x [[Apple A10 Fusion|Zephyr]] (A10) <br /> 3x [[Apple A10 Fusion|Zephyr]] (A10X)

|1.09-1.3&nbsp;GHz

|

|-

![[Apple A11|Monsoon]]

|rowspan="2"|2017

|ARMv8.2‑A<ref name="Apple-ARMv8.2">{{cite web|url=https://devstreaming-cdn.apple.com/videos/wwdc/2018/409t8zw7rumablsh/409/409_whats_new_in_llvm.pdf|title=Apple A11 New Instruction Set Extensions|publisher=Apple Inc.|date=June 8, 2018}}</ref>

|7-wide

|16

|{{Yes}}

|

|

|{{Yes|"big" <small>(In [[Apple A11]] paired with "LITTLE" [[Apple A11|Mistral]]<br />cores)</small>}}

|11

|3*128b

|10

|No

|No

|64 + 64<ref name="A11_A12_caches">{{cite web|url=https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/2|title=Measured and Estimated Cache Sizes|publisher=AnandTech|date=October 5, 2018}}</ref>

|8 MiB

|No

|2x [[Apple A11|Monsoon]]

|2.39&nbsp;GHz

|

|-

![[Apple A11|Mistral]]

|ARMv8.2‑A<ref name="Apple-ARMv8.2" />

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|10

|No

|No

|32 + 32<ref name="A11_A12_caches" />

|1&nbsp;MiB

|No

|4× [[Apple A11|Mistral]]

|1.19&nbsp;GHz

|

|-

![[Apple A12|Vortex]]

|rowspan="2"|2018

|ARMv8.3‑A<ref name="Apple-ARMv8.3">{{cite web|url=http://newosxbook.com/forum/viewtopic.php?f=11&t=19557|title=Apple A12 Pointer Authentication Codes|date=September 12, 2018|publisher=Jonathan Levin, @Morpheus|access-date=8 October 2018|archive-date=10 October 2018|archive-url=https://web.archive.org/web/20181010011352/http://newosxbook.com/forum/viewtopic.php?f=11&t=19557|url-status=dead}}</ref>

|7-wide

|16

|{{Yes}}

|

|

|{{Yes|"big" <small>(In [[Apple A12]]/[[Apple A12X]]/[[Apple A12Z]] paired with "LITTLE" [[Apple A12|Tempest]]<br />cores)</small>}}

|11

|3*128b

|7

|No

|No

|128 + 128<ref name="A11_A12_caches" />

|8 MiB

|No

|2x [[Apple A12|Vortex]] (A12) <br /> 4x [[Apple A12|Vortex]] (A12X/A12Z)

|2.49&nbsp;GHz

|

|-

![[Apple A12|Tempest]]

|ARMv8.3‑A<ref name="Apple-ARMv8.3" />

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|7

|No

|No

|32 + 32<ref name="A11_A12_caches" />

|2&nbsp;MiB

|No

|4x [[Apple A12|Tempest]]

|1.59&nbsp;GHz

|

|-

![[Apple A13|Lightning]]

|rowspan="2"|2019

|ARMv8.4‑A <ref name="Jonathan Levin, @Morpheus">{{cite web|url=http://newosxbook.com/ChangeLog.html#v2|title=A13 has ARMv8.4, apparently (LLVM project sources, thanks, @Longhorn)|publisher=Jonathan Levin, @Morpheus|date=March 13, 2020}}</ref>

|8-wide

|16

|{{Yes}}

|560

|

|{{Yes|"big" <small>(In [[Apple A13]] paired with "LITTLE" [[Apple A13|Thunder]]<br />cores)</small>}}

|11

|3*128b

|7

|No

|No

|128 + 128<ref name="A13_Thunder_caches">{{cite web|url=https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/2|title=The Apple A13 SoC: Lightning & Thunder|publisher=AnandTech|date=October 16, 2019}}</ref>

|8 MiB

|No

|2x [[Apple A13|Lightning]]

|2.65&nbsp;GHz

|

|-

![[Apple A13|Thunder]]

|ARMv8.4‑A <ref name="Jonathan Levin, @Morpheus"/>

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|7

|No

|No

|96 + 48<ref name="A13_caches">{{cite web|url=https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/3|title=The A13's Memory Subsystem: Faster L2, More SLC BW|publisher=AnandTech|date=October 16, 2019}}</ref>

|4 MiB

|No

|4x [[Apple A13|Thunder]]

|1.8&nbsp;GHz

|

|-

![[Apple A14|Firestorm]]

|rowspan="2"|2020

|ARMv8.5-A<ref name="LLVM Project">{{Cite web |title=LLVM Project (GitHub) |url=https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def |access-date=2022-09-25 |website=github.com |language=en |url-status=live }}</ref>

|8-wide<ref name="M1_A14">{{cite web|url=https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2|title=Apple Announces The Apple Silicon M1: Ditching x86 - What to Expect, Based on A14|publisher=AnandTech|date=November 10, 2020}}</ref>

|

|{{Yes}}

|630<ref>{{Cite web|last=Frumusanu|first=Andrei|title=Apple Announces The Apple Silicon M1: Ditching x86 - What to Expect, Based on A14|url=https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive|access-date=2020-11-25|website=www.anandtech.com}}</ref>

|

|{{Yes|"big" <small>(In [[Apple A14]] and [[Apple M1|Apple M1/M1 Pro/M1 Max/M1 Ultra]] paired with "LITTLE" [[Apple A14|Icestorm]]<br />cores)</small>}}

|14

|4*128b

|5

|No

|

|192 + 128

|8 MiB (A14)<br />12 MiB (M1)<br />24 MiB (M1 Pro/M1 Max)<br />48 MiB (M1 Ultra)

|No

|2x [[Apple A14|Firestorm]] (A14) <br /> 4x [[Apple A14|Firestorm]] (M1) <br />

6x or 8x [[Apple A14|Firestorm]] (M1 Pro)<br />

8x [[Apple A14|Firestorm]] (M1 Max)<br />

16x Firestorm (M1 Ultra)

|3.0-3.23&nbsp;GHz

|

|-

![[Apple A14|Icestorm]]

|ARMv8.5-A<ref name="LLVM Project"/>

|4-wide

|

|{{Yes}}

|110

|

|{{Yes|LITTLE}}

|7

|2*128b

|5

|No

|

|128 + 64

|4 MiB<br />8 MiB (M1 Ultra)

|No

|4x [[Apple A14|Icestorm]] (A14/M1) <br /> 2x [[Apple A14|Icestorm]] (M1 Pro/Max) <br /> 4x Icestorm (M1 Ultra)

|1.82-2.06&nbsp;GHz

|

|-

![[Apple A15|Avalanche]]

|rowspan="2"|2021

|ARMv8.5‑A<ref name="LLVM Project"/>

|8-wide

|

|{{Yes}}

|

|

|{{Yes|"big" <small>(In [[Apple A15]] and [[Apple M2]] paired with "LITTLE" [[Apple A15|Blizzard]]<br />cores)</small>}}

|14

|4*128b

|5

|No

|

|192 + 128

|12 MiB (A15)<br />16 MiB (M2)

|No

|2x [[Apple A15|Avalanche]] (A15) <br /> 4x [[Apple A15|Avalanche]] (M2)

|2.93-3.49&nbsp;GHz

|

|-

![[Apple A15|Blizzard]]

|ARMv8.5‑A<ref name="LLVM Project"/>

|4-wide

|

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|8

|2*128b

|5

|No

|

|128 + 64

|4 MiB

|No

|4x [[Apple A15|Blizzard]]

|2.02-2.42&nbsp;GHz

|

|-

![[Apple A16|Everest]]

|rowspan="2"|2022

|ARMv8.5‑A<ref name="LLVM Project"/>

|8-wide

|

|{{Yes}}

|

|

|{{Yes|"big" <small>(In [[Apple A16]] paired with "LITTLE" [[Apple A15|Blizzard]]<br />cores)</small>}}

|14

|4*128b

|5

|No

|

|192 + 128

|16 MiB

|No

|2x [[Apple A16|Everest]]

|3.46&nbsp;GHz

|

|-

![[Apple A16|Sawtooth]]

|ARMv8.5‑A<ref name="LLVM Project"/>

|4-wide

|

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|8

|2*128b

|5

|No

|

|128 + 64

|4 MiB

|No

|4x [[Apple A16|Sawtooth]]

|2.02&nbsp;GHz

|

|-

! rowspan="3" |[[Nvidia]]

![[Project Denver|Denver]]<ref name="Denver-Announce" /><ref name="linley-denver">{{cite web|url=http://www.linleygroup.com/mpr/article.php?id=11262|title=Denver Uses Dynamic Translation to Outperform Mobile Rivals|last1=Gwennap|first1=Linley|website=The Linley Group|access-date=24 April 2015}}</ref>

|2014

|ARMv8‑A

| 2-wide hardware<br />decoder, up to<br />7-wide variable-<br />length [[very long instruction word|VLIW]]<br />micro-ops

| 13

| {{Maybe|Not if the hardware<br />decoder is in use.<br />Can be provided<br />by dynamic software<br />translation into [[very long instruction word|VLIW]].}}

|

| Direct+<br />Indirect branch<br />prediction

| No

| 7

|

| 28

|No

|No

| 128 + 64

| 2&nbsp;MiB

| No

| {{dunno}}

|

![[Project Denver|Denver 2]]<ref>{{cite news|url=http://www.anandtech.com/show/10596/hot-chips-2016-nvidia-discloses-tegra-parker-details|title=Hot Chips 2016: NVIDIA Discloses Tegra Parker Details|last1=Ho|first1=Joshua|date=25 August 2016|access-date=25 August 2016|publisher=Anandtech}}</ref>

|2016

| ARMv8‑A

| {{dunno}}

| 13

| {{Maybe|Not if the hardware<br />decoder is in use.<br />Can be provided<br />by dynamic software<br />translation into [[very long instruction word|VLIW]].}}

|

| Direct+<br />Indirect branch<br />prediction

| "Super" <small>Nvidia's own implementation</small>

| {{dunno}}

|

| 16

|No

|No

| 128 + 64

| 2&nbsp;MiB

| No

| 2|| {{dunno}}

|

![[Project Denver|]]

|2018

| ARMv8.2‑A

| {{dunno}}

|

|

|

| Direct+<br />Indirect branch<br />prediction

|

| {{dunno}}

|

| 12

|No

|No

| 128 + 64

| 2&nbsp;MiB

| (4&nbsp;MiB @ 8 cores)

| 2 (+ 8)

| {{dunno}}

|

! [[Cavium]]

![[Cavium ThunderX|ThunderX]]<ref name="ARM server overview">{{cite news|last1=De Gelas|first1=Johan|title=ARM Challenging Intel in the Server Market|url=http://www.anandtech.com/show/8776/arm-challinging-intel-in-the-server-market-an-overview|access-date=8 March 2017|publisher=Anandtech|date=16 December 2014}}</ref><ref name="ThunderX_review">{{cite news|last1=De Gelas|first1=Johan|title=Investigating the Cavium ThunderX|url=http://www.anandtech.com/show/10353/investigating-cavium-thunderx-48-arm-cores|access-date=8 March 2017|publisher=Anandtech|date=15 June 2016}}</ref>

| 2014

| ARMv8-A || 2-wide || 9<ref name="ThunderX_review" /> || {{Yes}}<ref name="ARM server overview" />

| || {{Yes|Two-level}} || || {{dunno}}

| || 28

|No

|No|| 78 + 32<ref name="electronic-design" /><ref name="Cavium" />|| 16&nbsp;MiB<ref name="electronic-design" /><ref name="Cavium" />|| No || 8–16, 24–48 || {{dunno}}

|

! [[Cavium ThunderX2|ThunderX2]]<br /><ref>{{Cite web|url=https://fuse.wikichip.org/news/1316/a-look-at-caviums-new-high-performance-arm-microprocessors-and-the-isambard-supercomputer/|title=A Look at Cavium's New High-Performance ARM Microprocessors and the Isambard Supercomputer|date=2018-06-03|website=WikiChip Fuse|language=en-US|access-date=2019-06-17}}</ref><small>(ex. Broadcom Vulcan<ref>{{cite web|url=https://reviews.llvm.org/D30510|title=⚙ D30510 Vulcan is now ThunderX2T99|website=reviews.llvm.org}}</ref>)</small>

| 2018<ref>{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 256 Thread Arm Platforms Hit General Availability|url=https://www.servethehome.com/cavium-thunderx2-hits-general-availability/|access-date=10 May 2018|date=7 May 2018}}</ref>

| ARMv8.1-A<br /><ref>{{cite web|url=https://reviews.llvm.org/D21500|title=⚙ D21500 [AARCH64] Add support for Broadcom Vulcan|website=reviews.llvm.org}}</ref>|| 4-wide<br />"4 μops"<ref>https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf {{Bare URL PDF|date=March 2022}}</ref><ref>{{cite web|url=http://www.linleygroup.com/events/agenda.php?num=24&day=1|title=The Linley Group - Processor Conference 2013|website=www.linleygroup.com}}</ref>|| {{dunno}} || {{Yes}}<ref>{{cite web|url=http://www.cavium.com/ThunderX2_ARM_Processors.html|title=ThunderX2 ARM Processors- A Game Changing Family of Workload Optimized Processors for Data Center and Cloud Applications - Cavium|website=www.cavium.com}}</ref>

| || {{Yes|Multi-level}} || {{dunno}} || {{dunno}}

| || 16<ref name="Vulcan-Announce" />

|SMT4

|No|| 32 + 32<br />(data 8-way) || 256&nbsp;KiB<br />per core<ref name="tx2_bench">{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option|url=https://www.servethehome.com/cavium-thunderx2-review-benchmarks-real-arm-server-option/|access-date=10 May 2018|publisher=Serve the Home|date=9 May 2018}}</ref>|| 1&nbsp;MiB<br />per core<ref name="tx2_bench" />|| 16-32<ref name="tx2_bench" />|| {{dunno}}

|

! rowspan="1" | [[Marvell Technology Group|Marvell]]

! [[Marvell ThunderX3|ThunderX3]]

| 2020<ref name="thunderX3">{{cite news|last1=Frumusanu|first1=Andrei|title=Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor|url=https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor|date=16 March 2020}}</ref>

| ARMv8.3+<ref name="thunderX3" />|| 8-wide || {{dunno}} || {{Yes}}<br /> 4-wide dispatch

| || {{Yes|Multi-level}} || {{dunno}} || 7

| || 7<ref name="thunderX3" />

|SMT4<ref name="thunderX3" />

|{{dunno}} || 64 + 32 || 512&nbsp;KiB<br />per core || 90&nbsp;MiB || 60 || {{dunno}}

|

|-

! rowspan="4" | [[Applied Micro Circuits Corporation|Applied]]

[[Applied Micro Circuits Corporation|Micro]]

![[Applied Micro Circuits Corporation|Helix]]

| 2014 || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 40&nbsp;/&nbsp;28

|No

|No|| rowspan="3" | 32 + 32 (per core;<br />write-through<br />w/parity)<ref>{{cite news |url=http://anandtech.com/show/8588/armv8-goes-embedded-with-applied-micros-helix-socs |title=ARMv8 Goes Embedded with Applied Micro's HeliX SoCs |author=Ganesh T S |publisher=AnandTech|date=3 October 2014 |access-date=9 October 2014}}</ref>|| rowspan="3" | 256&nbsp;KiB shared<br />per core pair (with ECC) || 1&nbsp;MiB/core || 2, 4, 8 || {{dunno}}

|

|-

![[Applied Micro Circuits Corporation|X-Gene]]

| 2013

| {{dunno}} || 4-wide || 15 || {{Yes}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 40<ref>{{cite news |url=http://www.enterprisetech.com/2014/08/12/applied-micro-plots-x-gene-arm-server-future/ |title=Applied Micro Plots Out X-Gene ARM Server Future |first=Timothy Prickett |last=Morgan |publisher=Enterprisetech |date=12 August 2014 |access-date=9 October 2014}}</ref>

|No

|No|| 8&nbsp;MiB || 8 || 4.2

|

|-

! X-Gene 2

| 2015

| {{dunno}} || 4-wide || 15 || {{Yes}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 28<ref name="AT_XG3">{{cite news|last1=De Gelas|first1=Johan|title=AppliedMicro's X-Gene 3 SoC Begins Sampling|url=http://www.anandtech.com/show/11189/appliedmicro-x-gene-3-soc-starts-sampling|access-date=15 March 2017|publisher=Anandtech|date=15 March 2017}}</ref>

|No

|No|| 8&nbsp;MiB || 8 || 4.2

|

|-

! X-Gene 3<ref name="AT_XG3" />

| 2017

| {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 16

|No

|No|| {{dunno}} || {{dunno}} || 32&nbsp;MiB || 32 || {{dunno}}

|

|-

! rowspan="12" |[[Qualcomm]]

![[Kryo#Kryo (original)|Kryo]]

| 2015

| ARMv8-A || {{dunno}} || {{dunno}} || {{Yes}}

| || {{Yes|Two-level?}} || {{Yes|"big" or "LITTLE" <small><br />Qualcomm's own similar implementation</small>}} || {{dunno}}

| || 14<ref name="Kryo-ann">{{cite web|url=https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |title=Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute |publisher=Qualcomm |date=2 September 2015 |access-date=6 September 2015}}</ref>

|No

|No|| 32+24<ref>{{cite web|url=http://www.anandtech.com/show/9837/snapdragon-820-preview/|title=The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo|first=Ryan Smith, Andrei|last=Frumusanu}}</ref>|| 0.5–1 MiB || || 2+2 || 6.3

|

|-

! rowspan="2" |[[Kryo#Kryo 200 Series|Kryo 200]]

| rowspan="2" | 2016

| rowspan="2" |ARMv8-A

|2-wide

|11–12|| {{Yes}}<br /> 7-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}}

|| 7

|

| rowspan="2" |14 / 11 / 10 / 6 <ref name=":1">{{Cite news|url=https://www.anandtech.com/show/12420/snapdragon-845-performance-preview|title=The Snapdragon 845 Performance Preview: Setting the Stage for Flagship Android 2018|last=Smith|first=Andrei Frumusanu, Ryan|access-date=2018-06-11}}</ref>

| rowspan="2" |No

| rowspan="2" |No

|64 + 32/64?

|512&nbsp;KiB/Gold Core

| rowspan="2" |No

|4||1.8-2.45&nbsp;GHz

|

|-

|2-wide

|8|| {{No}}

|0

| Conditional+<br />Indirect branch<br />prediction | Conditional+<br />Indirect branch<br />prediction

|{{yes|LITTLE}}

|2

|

|8–64? + 8–64?

|256&nbsp;KiB/Silver Core

|4||1.8-1.9&nbsp;GHz

|

|-

! rowspan="2" |[[Kryo#Kryo 300 Series|Kryo 300]]

| rowspan="2" |2017

| rowspan="2" |ARMv8.2-A

|3-wide

|11–13|| {{Yes}}<br /> 8-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}}

||8

|

| rowspan="2" |10<ref name=":1" />

| rowspan="2" |No

| rowspan="2" |No

|64+64<ref name=":1" />

|256&nbsp;KiB/Gold Core

| rowspan="2" |2 MiB

|2, 4||2.0-2.95&nbsp;GHz

|

|-

|2-wide

|8|| {{No}}

|0

| Conditional+<br />Indirect branch<br />prediction | Conditional+<br />Indirect branch<br />prediction

| {{yes|LITTLE}}

|28

|

|16–64? + 16–64?

|128&nbsp;KiB/Silver

|4, 6||1.7-1.8&nbsp;GHz

|

|-

! rowspan="2" |[[Kryo#Kryo 400 Series|Kryo 400]]

| rowspan="2" |2018

| rowspan="2" |ARMv8.2-A

|4-wide

|11–13|| {{Yes}}<br /> 8-wide dispatch

| || {{Yes}} || {{Yes|big}}

|8

|

| rowspan="2" |11 / 8 / 7

| rowspan="2" |No

| rowspan="2" |No

|64 + 64

|512&nbsp;KiB/Gold Prime

256&nbsp;KiB/Gold

| rowspan="2" |2&nbsp;MiB

|2, 1+1, 4, 1+3|| 2.0-2.96&nbsp;GHz

|

|-

|2-wide

|8|| {{No}}

|0

| Conditional+<br />Indirect branch<br />prediction | Conditional+<br />Indirect branch<br />prediction

| {{yes|LITTLE}}

|2

|

|16–64? + 16–64?

|128&nbsp;KiB/Silver

|4, 6

|1.7-1.8&nbsp;GHz

|

|-

! rowspan="2" |[[Kryo|Kryo 500]]

| rowspan="2" |2019

| rowspan="2" |ARMv8.2-A

|4-wide

|11–13|| {{Yes}}<br /> 8-wide dispatch

| || {{Yes}} || {{Yes|big}}

|

|

| rowspan="2" |8 / 7

| rowspan="2" |No

|?

|

|512&nbsp;KiB/Gold Prime

256&nbsp;KiB/Gold

| rowspan="2" |3&nbsp;MiB

|2, 1+3

|2.0-3.2&nbsp;GHz

|

|-

|2-wide

|8|| {{No}}

|0

| Conditional+<br />Indirect branch<br />prediction | Conditional+<br />Indirect branch<br />prediction

|{{yes|LITTLE}}

|2

|

|?

|

|128&nbsp;KiB/Silver

|4, 6

|1.7-1.8&nbsp;GHz

|

|

|-

! rowspan="2" |[[Kryo|Kryo 600]]

| rowspan="2" |2020

| rowspan="2" |ARMv8.4-A

|4-wide

|11–13|| {{Yes}}<br /> 8-wide dispatch

| || {{Yes}} || {{Yes|big}}

|

|

| rowspan="2" |6 / 5

| rowspan="2" |No

|?

|64 + 64

|1024&nbsp;KiB/Gold Prime

512&nbsp;KiB/Gold

| rowspan="2" |4 MiB

|2, 1+3

|2.2-3.0&nbsp;GHz

|

|-

|2-wide

|8|| {{No}}

|0

| Conditional+<br />Indirect branch<br />prediction | Conditional+<br />Indirect branch<br />prediction

|{{yes|LITTLE}}

|2

|

|?

|

|128&nbsp;KiB/Silver

|4, 6

|1.7-1.8&nbsp;GHz

|

|

|-

! Falkor<ref name="Falkor sampling">{{cite news|last1=Shilov|first1=Anton|title=Qualcomm Demos 48-Core Centriq 2400 SoC in Action, Begins Sampling|url=http://www.anandtech.com/show/10918/qualcomm-demos-48core-centriq-2400-server-soc-in-action-begins-sampling|quote=In 2015, Qualcomm teamed up with Xilinx and Mellanox to ensure that its server SoCs are compatible with FPGA-based accelerators and data-center connectivity solutions (the fruits of this partnership will likely emerge in 2018 at best).|access-date=8 March 2017|publisher=Anandtech|date=16 December 2016}}</ref><ref name="Falkor">{{cite news|last1=Cutress|first1=Ian|title=Analyzing Falkor's Microarchitecture|url=http://www.anandtech.com/show/11737/analyzing-falkors-microarchitecture-a-deep-dive-into-qualcomms-centriq-2400-for-windows-server-and-linux |quote=The CPU cores, code named Falkor, will be ARMv8.0 compliant although with ARMv8.1 features, allowing software to potentially seamlessly transition from other ARM environments (or need a recompile). The Centriq 2400 family is set to be AArch64 only, without support for AArch32: Qualcomm states that this saves some power and die area, but that they primarily chose this route because the ecosystems they are targeting have already migrated to 64-bit. Qualcomm’s Chris Bergen, Senior Director of Product Management for the Centriq 2400, stated that the majority of new and upcoming companies have started off with 64-bit as their base in the data center, and not even considering 32-bit, which is a reason for the AArch64-only choice here. [..] Micro-op cache / L0 I-cache with Way prediction [..] The L1 I-cache is 64KB, which is similar to other ARM architecture core designs, and also uses 64-byte lines but with an 8-way associativity. To software, as the L0 is transparent, the L1 I-cache will show as an 88KB cache.|access-date=21 August 2017|publisher=Anandtech|date=20 August 2017}}</ref>

| 2017<ref>{{cite news|last1=Shrout|first1=Ryan|title=Qualcomm Centriq 2400 Arm-based Server Processor Begins Commercial Shipment|url=https://www.pcper.com/news/Processors/Qualcomm-Centriq-2400-Arm-based-Server-Processor-Begins-Commercial-Shipment|access-date=8 November 2017|publisher=PC Per|date=8 November 2017}}</ref>

| "[[ARMv8.1-A]] features";<ref name="Falkor" /> [[AArch64]]&nbsp;only <small>(not [[32-bit]])</small><ref name="Falkor" />|| 4-wide || 10–15 || {{yes|Yes<br />8-wide dispatch}}

| || {{Yes|Yes}} || {{dunno}} || 8

| || 10

|No

|24 KiB|| 88<ref name="Falkor" /> + 32 || 500KiB || 1.25MiB || 40-48 || {{dunno}}

|

|-

! rowspan="5" |[[Samsung]]

! M1<ref name=":3">{{cite web|url=http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed|title=Hot Chips 2016: Exynos M1 Architecture Disclosed|first=Joshua|last=Ho}}</ref><ref name=":4">{{cite web|url=http://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu|title=Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU|first=Andrei|last=Frumusanu}}</ref>

| 2016

| ARMv8-A || 4-wide || 13<ref name="AT_m3">{{cite news|last1=Frumusanu|first1=Andrei|title=The Samsung Exynos M3 - 6-wide Decode with 50%+ IPC Increase|url=https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture|access-date=25 January 2018|publisher=Anandtech|date=23 January 2018}}</ref>|| {{Yes}}<br /> 9-wide dispatch<ref name=exynosm1>{{cite web|last1=Frumusanu|first1=Andrei|title=Hot Chips 2016: Exynos M1 Architecture Disclosed|url=http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed|website=Anandtech|access-date=29 May 2017}}</ref>

|96

|| || {{Yes|big}} || 8

| || 14

|No

|No|| 64 + 32 || 2 MiB<ref>{{cite web|url=https://www.theregister.co.uk/2016/08/22/samsung_m1_core/|title='Neural network' spotted deep inside Samsung's Galaxy S7 silicon brain|website=[[The Register]] }}</ref>|| No || 4 || 2.6&nbsp;GHz

|

|-

!M2<ref name=":3" /><ref name=":4" />

|2017

|ARMv8-A

|4-wide

|

|

|100|| {{Yes|Two-level}} || {{Yes|big}}

|

|

|10

|No

|No

|64 + 64

|2 MiB

|No

|4

|2.3&nbsp;GHz

|

|-

! M3<ref name="AT_m3" /><ref>{{Cite web|url=https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive|title=Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive|last=Frumusanu|first=Andrei|website=www.anandtech.com|access-date=2019-06-17}}</ref>

| 2018

| ARMv8.2-A || 6-wide || 15 || {{Yes}}<br /> 12-wide dispatch

|228|| {{Yes|Two-level}} || {{Yes|big}} || 12

| || 10

|No

|No|| 64 + 64 || 512 KiB per core || 4096KB || 4 || 2.7&nbsp;GHz

|

|-

! M4<ref>{{Cite web|url=https://fuse.wikichip.org/news/2051/samsung-discloses-exynos-m4-changes-upgrades-support-for-armv8-2-rearranges-the-back-end/|title=Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End|last=Schor|first=David|date=2019-01-14|website=WikiChip Fuse|language=en-US|access-date=2019-06-17}}</ref>

|2019

|ARMv8.2-A

|6-wide

|15|| {{Yes}}<br /> 12-wide dispatch

|228|| {{Yes|Two-level}} || {{Yes|big}}

|12

|

|8 / 7

|No

|No

|64 + 64

|512 KiB per core

|3072KB

|2

|2.73&nbsp;GHz

|

|-

!M5<ref>{{Cite web|last=Frumusanu|first=Andrei|title=ISCA 2020: Evolution of the Samsung Exynos CPU Microarchitecture|url=https://www.anandtech.com/show/15826/isca-2020-evolution-of-the-samsung-exynos-cpu-microarchitecture|access-date=2021-01-24|website=www.anandtech.com}}</ref>

|2020

|ARMv8.2-A

|6-wide

| || {{Yes}}<br /> 12-wide dispatch

|228|| {{Yes|Two-level}} || {{Yes|big}}

|

|

|7

|No

|No

|64 + 64

|512 KiB per core

|3072KB

|2

|2.73&nbsp;GHz

|

|-

! [[Fujitsu]]

! [[Fujitsu A64FX|A64FX]]<ref>{{citation|title=Fujitsu High Performance CPU for the Post-K Computer|url=https://www.fujitsu.com/global/documents/solutions/business-technology/tc/catalog/20180821hotchips30.pdf|access-date=16 Sep 2019|date=2018-07-21}}</ref><ref>{{citation|title=Arm A64fx and Post-K: Game Changing CPU & Supercomputer for HPC and its Convergence of with Big Data / AI|url=https://www.hpcuserforum.com/presentations/april2019/Rikenmatsuoka.pdf|access-date=16 Sep 2019|date=2019-04-03}}</ref>

|2019

|ARMv8.2-A

|4/2-wide

|7+ || {{Yes}}<br />5-way?

| || {{Yes}} || n/a

|8+

|2*512b<ref>{{Cite web|title=Fujitsu Successfully Triples the Power Output of Gallium-Nitride Transistors - Fujitsu Global|url=https://www.fujitsu.com/global/about/resources/news/press-releases/2018/0822-02.html|access-date=2020-11-23|website=www.fujitsu.com}}</ref>

|7

|No

|No

|64 + 64

|8MiB per 12+1 cores

|No

|48+4

|1.9&nbsp;GHz+; 15GF/W+.

|

|-

! [[HiSilicon]]

! TaiShan V110<ref>{{Cite web|url=https://fuse.wikichip.org/news/2274/huawei-expands-kunpeng-server-cpus-plans-smt-sve-for-next-gen/|title=Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen|last=Schor|first=David|date=2019-05-03|website=WikiChip Fuse|language=en-US|access-date=2019-12-13}}</ref>

|2019

|ARMv8.2-A

|4-wide

|?

|{{Yes}}

|

|

|n/a

|8

|7

|

|No

|No

|64 + 64

|512 KiB per core

|1 MiB per core

|?

|?

|

|-

! Company

! Released

! Revision

! Decode

![[Instruction pipeline|Pipeline]]<br />depth

! colspan="2" |[[Out-of-order execution|Out-of-order<br />execution]]

![[Branch predictor|Branch<br />prediction]]

![[ARM big.LITTLE|big.LITTLE]] role

! <br />

![[SIMD instruction|SIMD]]

![[Semiconductor device fabrication|Fab]]<br />(in [[Nanometer|nm]])

![[Simultaneous multithreading|Simult. MT]]

![[CPU cache|L0 cache]]

![[CPU cache|L1 cache]]<br />[[Instruction cache|Instr]]&nbsp;+&nbsp;[[Data cache|Data]]<br />(in [[Kibibyte|KiB]])

! Core

![[Dhrystone#Results|DMIPS/MHz]]

!ARM part number (in the main ID register)

* [[ of ]]

* [[ of ]]

==Notes==

{{reflist|group=note}}

==References==

{{Reflist|32em|refs=

<ref name=A7-A15-execution-ports>{{Cite web|url=http://www.arm.com/files/downloads/big_LITTLE_Final_Final.pdf|title=big.LITTLE processing with ARM Cortex-A15 & Cortex-A7|website=www.arm.com|publisher=[[ARM Holdings]]|access-date=6 August 2014|archive-url=https://web.Archive.org/web/20131017064722/http://www.arm.com/files/downloads/big_LITTLE_Final_Final.pdf|archive-date=17 October 2013|url-status=dead}}</ref>

<ref name=A8-execution-ports>{{Cite web|url=http://processors.wiki.TI.com/index.php/Cortex-A8_Architecture#Cortex-A8_Pipeline_Diagram|title=Cortex-A8 architecture|website=processors.wiki.TI.com|publisher=[[Texas Instruments]]|access-date=6 August 2014|archive-url=https://web.Archive.org/web/20140808144144/http://processors.wiki.TI.com/index.php/Cortex-A8_Architecture#Cortex-A8_Pipeline_Diagram|archive-date=8 August 2014|url-status=dead}}</ref>

<ref name=A9-whitepaper>{{Cite web|url=http://www.arm.com/files/pdf/armcortexa-9processors.pdf|title=The ARM Cortex-A9 processors|website=www.arm.com|publisher=[[ARM Holdings]]|access-date=6 August 2014|archive-url=https://web.Archive.org/web/20141117060156/http://www.arm.com/files/pdf/ARMCortexA-9Processors.pdf|archive-date=17 November 2014|url-status=dead}}</ref>

<ref name=Snapdragon-Krait>{{Cite web|first=Brian|last=Klug|url=http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture|title=Qualcomm's new Snapdragon S4: MSM8960 & Krait architecture explored|website=www.anandtech.com|publisher=[[Anandtech]]|date=7 October 2011|access-date=6 August 2014}}</ref>

<ref name=Cortex-A9>{{Cite web|url=http://www.arm.com/products/processors/cortex-a/cortex-a9.php|title=Cortex-A9 processor|website=www.arm.com|publisher=[[ARM Holdings]]|access-date=15 September 2014}}</ref>

<ref name=Cortex-A7>{{Cite web|url=http://www.arm.com/products/processors/cortex-a/cortex-a7.php|title=Cortex-A7 processor|website=www.arm.com|publisher=[[ARM Holdings]]|access-date=1 June 2016}}</ref>

<ref name=Virtualization-support>{{Cite web|url=https://www.arm.com/products/processors/technologies/virtualization-extensions.php|title=ARM processor hardware virtualization support|website=www.arm.com|publisher=[[ARM Holdings]]|access-date=1 June 2016}}</ref>

<ref name=Cortex-A15>{{Cite web|url=http://www.arm.com/products/processors/cortex-a/cortex-a15.php|title=Cortex-A15 processor|website=www.arm.com|publisher=[[ARM Holdings]]|access-date=9 August 2016}}</ref>

<ref name=Cortex-A17>{{Cite web|url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0535c/DDI0535C_cortex_a17_r1p1_trm.pdf|title=ARM Cortex-A17 MPCore processor technical reference manual|website=infocenter.arm.com|publisher=[[ARM Holdings]]|access-date=18 September 2014}}</ref>

<ref name="AnandTech-iPhone5s-A7">{{cite web

|first=Anand

|last=Lal Shimpi

|url=http://anandtech.com/show/7335/the-iphone-5s-review/2

|title=The iPhone 5s Review: A7 SoC Explained

|publisher=AnandTech

|date=17 September 2013

|access-date=3 July 2014}}</ref>

<ref name="AnandTech-iPhone5s-64-bit">{{cite web

|first=Anand

|last=Lal Shimpi

|url=http://anandtech.com/show/7335/the-iphone-5s-review/4

|title=The iPhone 5s Review: The Move to 64-bit

|date=17 September 2013

|publisher=AnandTech

|access-date=3 July 2014}}</ref>

<ref name="AnandTech-Cyclone">{{cite web

|first=Anand

|last=Lal Shimpi

|url=http://www.anandtech.com/show/7910/apples-cyclone-microarchitecture-detailed

|title=Apple's Cyclone Microarchitecture Detailed

|publisher=AnandTech

|date=31 March 2014

|access-date=3 July 2014}}</ref>

<ref name="Chipworks-A7">{{cite web

|first=Sinjin

|last=Dixon-Warren

|url=http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/

|title=Samsung 28nm HKMG Inside the Apple A7

|publisher=Chipworks

|date=20 January 2014

|access-date=3 July 2014

|archive-url=https://web.archive.org/web/20140406213924/http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/

|archive-date=6 April 2014

|url-status=dead

}}</ref>

<ref name="Denver-Announce">{{cite web

|first=Nick

|last=Stam

|url=http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/

|title=Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android

|publisher=NVidia

|date=11 August 2014

|access-date=11 August 2014}}</ref>

<ref name="Vulcan-Announce">{{cite web

|url=http://www.broadcom.com/press/release.php?id=s797235

|title=Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture

|publisher=Broadcom

|date=15 October 2013

|access-date=11 August 2014}}</ref>

<ref name="electronic-design">{{cite web

|url=http://electronicdesign.com/microprocessors/64-bit-cortex-platform-take-x86-servers-cloud

|title=64-bit Cortex Platform To Take On x86 Servers In The Cloud

|publisher=electronic design

|date=5 June 2014

|access-date=7 February 2015}}</ref>

<ref name="Cavium">{{cite web

|url=http://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf

|title=ThunderX_CP™ Family of Workload Optimized Compute Processors

|publisher=Cavium

|date=2014

|access-date=7 February 2015}}</ref>

<ref name="TSMC-HiSilicon-16nm">{{cite web

|url=http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=8821&language=E

|title=TSMC Delivers First Fully Functional 16FinFET Networking Processor

|publisher=TSMC

|date=25 September 2014

|access-date=19 February 2015}}</ref>

<ref name="AnandTech-Twister">{{cite web

|first1= Joshua

|last1=Ho

|first2=Ryan

|last2=Smith

|url=http://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/4

|title=The Apple iPhone 6s and iPhone 6s Plus Review

|publisher=AnandTech

|date=2 Nov 2015

|access-date= 13 Feb 2016}}</ref>

}}