Skip to content
View honorpeter's full-sized avatar
💭
I may be slow to respond.
💭
I may be slow to respond.

Block or report honorpeter

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. haddoc2 haddoc2 Public

    Forked from DreamIP/haddoc2

    Caffe to VHDL - by DREAM research group

    VHDL 2

  2. cnn_open cnn_open Public

    Forked from lulinchen/cnn_open

    A hardware implementation of CNN, written by Verilog and synthesized on FPGA

    Coq 2 1

  3. FPGA-Accelerator-for-AES-LeNet-VGG16 FPGA-Accelerator-for-AES-LeNet-VGG16 Public

    Forked from zhan6841/FPGA-Accelerator-for-AES-LeNet-VGG16

    FPGA/AES/LeNet/VGG16

    Verilog 2 1

  4. LeNet-on-Zynq LeNet-on-Zynq Public

    Forked from flymin/LeNet-on-Zynq

    Simulating implement of LeNet network on Zynq-7020 FPGA

    VHDL 2

  5. FPGA FPGA Public

    Forked from HDCOE/FPGA

    C++ 2

  6. dnnweaver dnnweaver Public

    Forked from ZixuanJiang/dnnweaver

    fork from bitbucket.org/hsharma35/dnnweaver.public

    Verilog 2