1,433
questions
1
vote
1
answer
35
views
(Cortex M4) Bad section alignment in ELF file
we have a strange issue on a Cortex M4 MCU. The compiled Firmware works if the binary is loaded with ST-LINK in the correct section, but using C-Lion and OpenOcd, The FW load operation, load also the ...
1
vote
0
answers
27
views
DebugMon_Handler not triggered after configuring DWT (Data Watchpoint and Trace) to look for memory writes. (cortex-M33)
I am using the following code to configure the DWT(Data Watchpoint and Trace) and test it in Arm Development Studio. When using a Cortex-M4 or Cortex-M3, it triggers the DebugMon_Handler, but when ...
- 11
1
vote
0
answers
19
views
gnu ld linker script LONG() not placing value as expected (ARM Cortex-M3) [duplicate]
gnu .ld linker script --
I have added a MEMORY definition to hold a checksum:
_CRC_Value = 0x12345678;
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K
FLASH (rx) : ORIGIN = ...
1
vote
1
answer
36
views
How does ld decide the alignment of a section?
I crosscompile for cortex M microcontroller using arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi
The .bss has 2KB alignment
objdump:
Idx Name Size VMA LMA File off ...
- 1,438
1
vote
0
answers
17
views
ld merge all `*.str1.4` strings
I crosscompile for cortex M microcontroller using arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi
I compile using -fdata-sections and link using -Wl,--gc-sections -Wl,--sort-section=alignment
In map ...
- 1,438
2
votes
1
answer
70
views
gcc thumb2 inline assembly for fixed point conversion
I would like to write some gcc inline assembly for armv7em on Cortex-M7 to perform conversion between floating point numbers and fixed point numbers. ARM provides the vcvt instruction with #fbits to ...
- 21
1
vote
2
answers
63
views
Debug Application via SWD on Cortex-M Starting At FLASH Address Besides 0x00
I have used multiple Cortex M parts in the past, primarily using IAR as my IDE. I am currently developing a project for a Cortex M0+ part using an Eclipse-based IDE (Infineon ModusToolbox).
I'd like ...
- 433
0
votes
0
answers
32
views
cortex-m4 core clocking on st32f4 example using cmsis library
I ask for a review of the code for basic clocking of the stm32f401ccu core, for simple blinking of the LED.
void ClockInit(void){
//RCC->CR = 0x0000XX81;
RCC->CR |= (1 << ...
0
votes
1
answer
86
views
How to make my address add in every interrupt function?
First of all, I use arm cm3 core chips and the function of my codes is Shift operation. For example, UART receive "f0", save "0f" to the corresponding address. Codes are below.
...
1
vote
0
answers
33
views
Ensure Access to Vector Table for Both Bootloader and Application
I have a custom board that I am implementing a bootloader and application for based on an Infineon PSoC4 MAX device (Cortex M0 core). The bootloader is located in FLASH starting at address 0x00, while ...
- 433
0
votes
0
answers
13
views
No output for CAN protocol configuration on the Tiva TM4C1294ncpdt board using direct register manipulation
#include \<stdint.h\>
#include "tm4c1294ncpdt.h"
// Functions
void Config_msg_Obj(void);
void delay(unsigned int i);
void CAN_Init(void)
{
SYSCTL_RCGCCAN_R = 0x02; // ...
1
vote
0
answers
14
views
Does the Cortex-M55 Processor Support Shareable and Cacheable Attributes Simultaneously?
I was looking at the Cortex-M55 TRM document and came across the following statement:
'Normal shareable cacheable attributes are converted to Normal Shareable Noncacheable by the processor' (...
- 11
0
votes
2
answers
35
views
Why stepping debug failed with cc2538dk on Contiki-NG, but success on RIOT?
I have a question about debugging with cc2538 on Contiki-NG.
I'm testing the 6LoWPAN function on both RIOT and Contiki-NG. While stepping through the code during debugging, RIOT works fine, but ...
- 21
1
vote
1
answer
89
views
Local variable allocation crashes the stack in embedded C on cortexm4 and operating system
Details: embedded C, cortex M4 with operating system (RTX Kernel), compiled with ARM Compiler V5.06 update6 and Microlib.
Inside a periodic task there are some functons call, one is a debug function:
/...
- 317
2
votes
0
answers
80
views
ARM Cortex M4 context switching: How does the hardware know where xPSR, PC, LR, R12, R3-R0 are on the stack?
I'm working on a context switching mechanism for my RTOS which runs on Cortex-Ms.
When I initialize a task's stack, I have it like this
Then, I decrement the stack pointer 8 times to fit R11-R4.
I ...
- 33